Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Defect-oriented test scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test wrapper and test access mechanism co-optimization for system-on-chip
Proceedings of the IEEE International Test Conference 2001
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
Testing Reusable IP - A Case Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
ETW '03 Proceedings of the 8th IEEE European Test Workshop
IEEE Transactions on Computers
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The long and increasing test application time for modular core-based system-on-chips is a major problem, and many approaches have been developed to deal with the problem. Different from previous approaches, where it is assumed that all tests will be performed until completion, we consider the cases where the test process is terminated as soon as a defect is detected. Such abort-on-fail testing is common practice in production test of chips. We define a model to compute the expected test time for a given test schedule in an abort-on-fail environment. We have implemented three scheduling techniques and the experimental results show a significant test time reduction (up to 90%) when making use of an efficient test scheduling technique that takes defect probabilities into account.