Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme
Authors:
Marie-Lise Flottes;Julien Pouget;Bruno Rouzeyre
Affiliations:
-;-;-
Venue:
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies