Test in the Emerging Intellectual Property Business
IEEE Design & Test
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
An Effective BIST Scheme for Datapaths
Proceedings of the IEEE International Test Conference on Test and Design Validity
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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IEEE Transactions on Computers
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
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ETW '00 Proceedings of the IEEE European Test Workshop
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IEEE Transactions on Computers
Defect-Aware SOC Test Scheduling
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Journal of Electronic Testing: Theory and Applications
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test environment for embedded cores-based system-on-chip (soc): development and methodologies
MIC'06 Proceedings of the 25th IASTED international conference on Modeling, indentification, and control
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs
IEEE Transactions on Computers
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
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This paper discusses the test strategies that can beemployed for testing reusable Intellectual Property (IP).A typical System on Chip (SoC) design carried out atARM is presented as a case study. It highlights thechallenges faced when integrating IP blocks from diversesources. A hybrid approach was found to be the mostpragmatic solution, mixing bus-based, functional, scanand at-speed testing.The paper concludes with a look at how the task oftesting reusable IP will benefit from industrystandardisation efforts.