Embedded Test and Debug of Full Custom and Synthesizable Microprocessor Cores

Authors:
Andrew Burdass;Gary Campbell;Richard Grisenthwaite;David Gwilt;Peter Harrod;Richard York
Affiliations:
-;-;-;-;-;-
Venue:
ETW '00 Proceedings of the IEEE European Test Workshop
Year:
2000

Citing 2
Cited 3

AMBA: Enabling Reusable On-Chip Designs

IEEE Micro
Testing Reusable IP - A Case Study

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Software-based self-testing with multiple-level abstractions for soft processor cores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid software-based self-testing methodology for embedded processor

Proceedings of the 2008 ACM symposium on Applied computing
Effective hybrid test program development for software-based self-testing of pipeline processor cores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

This paper compares and contrasts two very different approaches to testing cached CPU macro-cells that are typically embedded in a System on Chip (SoC). One uses a test bus to apply functional vectors, while the other uses a combination of scan insertion, memory BIST and test collars. IP protection issues and non-intrusive tracing are also discussed.