A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Embedded Test and Debug of Full Custom and Synthesizable Microprocessor Cores
ETW '00 Proceedings of the IEEE European Test Workshop
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective Software Self-Test Methodology for Processor Cores
Proceedings of the conference on Design, automation and test in Europe
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid-SBST Methodology for Efficient Testing of Processor Cores
IEEE Design & Test
A Software-Based Test Methodology for Direct-Mapped Data Cache
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an effective hybrid test program for the software-based self-testing (SBST) of pipeline processor cores. The test program combines a deterministically developed program which explores different levels of processor core information and a block-based random program which consists of a combination of in-order instructions, random-order instructions, return instructions, as well as instruction sequences used to trigger exception/interrupt requests. Due to the complementary nature of this hybrid test program, it can achieve processor fault coverage that is comparable to the performance of the conventional scan chain method. The test response observation methods and their impacts on fault coverage are also investigated. We present the concept of micro observation versus macro observation and show that the most effective method of using SBST is through a multiple input signature register connected to the processor local bus, while conventional methods that observe only the program results in the memory lead to significantly less processor fault coverage.