Effective Software Self-Test Methodology for Processor Cores

  • Authors:
  • N. Kranitis;A. Paschalis;D. Gizopoulos;Y. Zorian

  • Affiliations:
  • Department of Informatics & Telecommunications, University of Athens, Greece;Department of Informatics & Telecommunications, University of Athens, Greece;Department of Informatics, University of Piraeus, Greece;LogicVision, San Jose, CA

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2002

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Abstract

Software self-testing for embedded processor coresbased on their instruction set, is a topic of increasinginterest since it provides an excellent test resourcepartitioning technique for sharing the testing task ofcomplex Systems-on-Chip (SoC) between slow,inexpensive testers and embedded code stored in memorycores of the SoC. We introduce an efficient methodologyfor processor cores self-testing which requires knowledgeof their instruction set and Register Transfer (RT) leveldescription. Compared with functional testingmethodologies proposed in the past, our methodology ismore efficient in terms of fault coverage, test code sizeand test application time. Compared with recent softwarebased structural testing methodologies for processorcores, our methodology is superior in terms of testdevelopment effort and has significantly smaller code sizeand memory requirements, while virtually the same faultcoverage is achieved with an order of magnitude smallertest application time.