The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Retargetable self-test program generation using constraint logic programming
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Functional verification of the equator MAP1000 microprocessor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Superscalar Processor Validation at the Microarchitecture Level
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective Software Self-Test Methodology for Processor Cores
Proceedings of the conference on Design, automation and test in Europe
Automatic Test Program Generation: A Case Study
IEEE Design & Test
Code Generation for Functional Validation of Pipelined Microprocessors
Journal of Electronic Testing: Theory and Applications
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores
MTV '04 Proceedings of the Fifth International Workshop on Microprocessor Test and Verification
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Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Currently, Software-Based Self-Test (SBST) is becoming an attractive test solution since it guarantees high fault coverage figures, runs at-speed, and matches core test requirements while exploiting low-cost ATEs. However, automatically generating test programs is still an open problem. This paper presents a novel approach for test program generation, that couples evolutionary techniques with hardware acceleration. The methodology was evaluated targeting a 5-stage pipelined processor implementing a SPARCv8 microprocessor core.