Hybrid BIST optimization using reseeding and test set compaction

Authors:
Gert Jervan;Elmet Orasson;Helena Kruus;Raimund Ubar
Affiliations:
Department of Computer Engineering, Tallinn University of Technology, Raja 15, Tallinn 12618, Estonia;Department of Computer Engineering, Tallinn University of Technology, Raja 15, Tallinn 12618, Estonia;Department of Computer Engineering, Tallinn University of Technology, Raja 15, Tallinn 12618, Estonia;Department of Computer Engineering, Tallinn University of Technology, Raja 15, Tallinn 12618, Estonia
Venue:
Microprocessors & Microsystems
Year:
2008

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Abstract

Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper, we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with pre-computed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems.