Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test set compaction for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing concurrent test time in SoC's by balancing resource usage
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Optimization of Test Accesses with a Combined BIST and External Test Scheme
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process
IEEE Transactions on Computers
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Hybrid BIST optimization using reseeding and test set compaction
Microprocessors & Microsystems
Test time minimization for hybrid BIST of core-based systems
Journal of Computer Science and Technology
Hi-index | 0.00 |