Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and minimization of test time in a combined BIST and external test approach
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a novel test scheduling algorithm for embedded core-based SoC's. Given a system integrated with a set of cores and a set of test resources, we select a test for each core from a set of alternative test sets, and schedule it in a way that evenly balances the resource usage, and ultimately reduce the test application time. Furthermore, we propose a novel approach that groups the cores and assigns higher priority to those with smaller number of alternate test sets. In addition, we also extend the algorithm to allow multiple test sets selection from a set of alternatives to facilitate testing for various fault models.