System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Using March Tests to Test SRAMs
IEEE Design & Test
Mapping and Repairing Embedded-Memory Defects
IEEE Design & Test
Modeling application specific memories
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Merged Dram-Logic In The Year 2001
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Memory Generator Method for Sizing Transistors in RAM/ROM Blocks
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
A Widely Configurable EPROM Memory Compiler for Embedded Applications
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Rambist builder: a methodology for automatic built-in self-test design of embedded rams
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimizing concurrent test time in SoC's by balancing resource usage
Proceedings of the 12th ACM Great Lakes symposium on VLSI
ACM Transactions on Embedded Computing Systems (TECS)
On-Chip Clock Faults' Detector
Journal of Electronic Testing: Theory and Applications
Test and Repair of Large Embedded DRAMs: Part 1
ITC '01 Proceedings of the 2001 IEEE International Test Conference
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology
Journal of Electronic Testing: Theory and Applications
Extending boundary-scan to perform a memory built-in self-test
ICC'05 Proceedings of the 9th International Conference on Circuits
Partial product reduction by using look-up tables for M×N multiplier
Integration, the VLSI Journal
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Vccmin fault-tolerant cache with highly predictable performance
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
FPGA implementation of microcode-based and FSM-based memory built-in self test controllers
ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache
Proceedings of the 48th Design Automation Conference
Mathematical model of stored logic based computation
Mathematical and Computer Modelling: An International Journal
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Large on-chip memories are desirable but difficult to implement. Challenges range from design automation to fabrication to test algorithms and memory redundancy and repair.