Proceedings of the 27th annual international symposium on Computer architecture
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
Power4 System Design for High Reliability
IEEE Micro
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pin: building customized program analysis tools with dynamic instrumentation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Memory mapped ECC: low-cost error protection for last level caches
Proceedings of the 36th annual international symposium on Computer architecture
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Improving cache lifetime reliability at ultra-low voltages
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
ZerehCache: armoring cache architectures in high defect density technologies
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Low Vccmin fault-tolerant cache with highly predictable performance
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Reducing cache power with low-cost, multi-bit error-correcting codes
Proceedings of the 37th annual international symposium on Computer architecture
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches
Proceedings of the 49th Annual Design Automation Conference
Asymmetric-access aware optimization for STT-RAM caches with process variations
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Efficient cache architectures for reliable hybrid voltage operation using EDC codes
Proceedings of the Conference on Design, Automation and Test in Europe
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Cache is a roadblock towards low supply voltage (Vcc). It is mainly because low Vcc incurs process variation-induced bit errors in large SRAM in cache. Existing approaches for low Vcc cache suffer from low performance due to reduced effective capacity, long latency to correct errors, and increased misses due to accesses to faulty words. In our work, we propose a word-level sub-block disable-based method which increases the utilization of available cache capacity. Our key idea is to minimize accesses to faulty words. To do that, we propose utilizing access behavior history in allocating cache resource with faulty words. In addition, we propose remapping cache words inside of cache line in order to better match both access and error patterns. Experimental results show that the proposed method gives average 21.8% (up to 34.0%) performance improvement with a small area overhead in L1 and L2 caches.