Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Design and algorithms for parallel testing of random access and content addressable memories
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Asynchronous transfer mode: solution for broadband ISDN
Asynchronous transfer mode: solution for broadband ISDN
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
Functional test for shifting-type FIFOs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An effective BIST scheme for ring-address type FIFOs
ITC'94 Proceedings of the 1994 international conference on Test
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Test algorithms for static double-buffered RAMs and pointer-addressed memories (PAMs) are presented. The reasons why test algorithms for single-buffered memories are inadequate to test double-buffered memories (DBMs) are discussed. To obtain a realistic fault model, the authors perform an inductive fault analysis on the DBM cells. They also show that the address generation method imposes different requirements on the test algorithms.