An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Effective march algorithms for testing single-order addressed memories
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
Using March Tests to Test SRAMs
IEEE Design & Test
An Effective BIST Scheme for Ring-Address Type FIFOs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Towards a Uniform Notation for Memory Tests
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
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FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing use of FIFOs, as a stand-alone chip or as embedded macros in ASICs, generic algorithms are needed to test FIFOs. This paper addresses the problem of testing the widely available shifting-type FIFOs; it introduces specific fault models and a set of generic tests which have a test length of O(n) and can be used for the stand-alone chip as well as for the embedded macro version of the FIFO.