Design and algorithms for parallel testing of random access and content addressable memories

Authors:
P. Mazumder;J. H. Patel;W. K. Fuchs
Affiliations:
-;-;-
Venue:
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Year:
1987

Citing 0
Cited 7

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Verification of CAM Tests for Input Stuck-at Faults

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Functional Testing of Content-Addressable Memories

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An on-chip double-bit error-correcting code for three- dimensional dynamic random-access memory

ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing

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Abstract

This paper presents a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for CAMs and RAMs are developed for a broad class of pattern sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design for testability strategy allows an entire w word CAM to be read in just one operation with a resulting speed up in testing as high as w. In the case of an n bit RAM, the improvement in test efficiency is by a factor of &Ogr;(√n). The overall reduction in testing time is considerable for large size memories.