Design and algorithms for parallel testing of random access and content addressable memories
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Parallel testing of parametric faults in a DRAM
Proceedings of the fifth MIT conference on Advanced research in VLSI
Finite geometries
Design of Multi-Invariant Data Structures for Robust Shared Accesses in Multiprocessor Systems
IEEE Transactions on Software Engineering
Implementation and performance assessment of multilevel data structures
COMPSAC '97 Proceedings of the 21st International Computer Software and Applications Conference
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Construction and Analysis of Augmented Time Compactors
Journal of Electronic Testing: Theory and Applications
Hi-index | 14.98 |
Most current-generation multimegabit dynamic random-access memory (DRAM) chips use three-dimensional storage capacitors where the charge is stored on a vertically integrated trench-type structure and are highly vulnerable to alpha particles, which frequently create plasma shorts between two adjoining trench capacitors on the same word line, resulting in uncorrectable double-bit soft errors. The author presents a systematic study of soft-error related problems and discusses methodologies for correcting single-bit and double-bit memory-cell upsets by using on-chip error-correcting-code (ECC) circuits. By modifying the product code, an effective coding scheme has been designed that can be integrated within a DRAM chip to correct double-bit errors. It is demonstrated that the reliability of a memory chip can be improved by several million times by integrating the proposed circuit. The area and timing overhead are calculated and compared with those of memory chips without any ECC and chips with single-error-correcting (SEC) codes. The ability of the circuit to correct soft errors in the presence of multiple-bit errors is analyzed.