IEEE Transactions on Computers
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
Design of compactors for signature-analyzers in built-in self-test
Proceedings of the IEEE International Test Conference 2001
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Proceedings of the IEEE International Test Conference 2001
IEEE Design & Test
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Compactor Independent Direct Diagnosis
ATS '04 Proceedings of the 13th Asian Test Symposium
Synthesis of X-Tolerant Convolutional Compactors
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
ITC '04 Proceedings of the International Test Conference on International Test Conference
X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
Modular Compactor of Test Responses
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Constructing Augmented Multimode Compactors
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
Identification of failing tests with cycling registers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Diagnosis of Failing Scan Cells through Orthogonal Response Compaction
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finite memory test response compactors for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault Diagnosis With Convolutional Compactors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a procedure for constructing time compactors based on a new 3-dimensional augmented product code is presented. Accordingly, augmented time compactors are constructed by assigning a unique triplet to each scan chain and calculating at least four sets of parity check bits. Parity check bits of each set are XORed into stages of one or more multi-input shift registers. The proposed method allows constructing different classes of time compactors directly based on the coding theory. The constructed augmented time compactors outperform the most advanced time compactors of each respective class. All constructed compactor schemes are strictly defined and establish a clear baseline for future development in this area.