Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
X-Tolerant Test Response Compaction
IEEE Design & Test
Test response compactor with programmable selector
Proceedings of the 43rd annual Design Automation Conference
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
IEEE Design & Test
GECOM: test data compression combined with all unknown response masking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Study on Expansion of Convolutional Compactors over Galois Field
IEICE - Transactions on Information and Systems
X-tolerant Test Data Compaction with Accelerated Shift Registers
Journal of Electronic Testing: Theory and Applications
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fully X-tolerant, very high scan compression
Proceedings of the 47th Design Automation Conference
A combinatorial approach to X-tolerant compaction circuits
IEEE Transactions on Information Theory
Design and analysis of compact dictionaries for diagnosis in scan-BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Construction and Analysis of Augmented Time Compactors
Journal of Electronic Testing: Theory and Applications
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Stochastic coding is used to design X-tolerant signature analyzers that can detect defective chips even in the presence of unknown logic values (X's). These signature analyzers can be used for Built-In-Self-Test applications and test data compression. Application of this technique to industrial designs shows that thousands of X's can be tolerated while reducing test response data volume by 50 to 2,000 times compared to traditional scan, with practically no impact on test quality.