Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Response compaction with any number of unknowns using a new LFSR architecture
Proceedings of the 42nd annual Design Automation Conference
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimized integration of test compression and sharing for SOC testing
Proceedings of the conference on Design, automation and test in Europe
Scan Test Response Compaction Combined with Diagnosis Capabilities
Journal of Electronic Testing: Theory and Applications
DX-compactor: distributed X-compaction for SoCs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A combinatorial approach to X-tolerant compaction circuits
IEEE Transactions on Information Theory
Masking of X-Values by Use of a Hierarchically Configurable Register
Journal of Electronic Testing: Theory and Applications
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
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Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression techniques attempt to do more testing with fewer bits. This article summarizes one such method, X-compact, which addresses how unknowns, the bane of compression and logic BIST techniques, are eliminated.