X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
X-Tolerant Test Response Compaction
IEEE Design & Test
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
Unknown blocking scheme for low control data volume and high observability
Proceedings of the conference on Design, automation and test in Europe
Accelerated Shift Registers for X-tolerant Test Data Compaction
ETS '08 Proceedings of the 2008 13th European Test Symposium
Highly X-Tolerant Selective Compaction of Test Responses
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
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In this paper we consider masking of unknowns (X-values) for VLSI circuits. We present a new hierarchical method of X-masking which is a major improvement of the method proposed in [4], called WIDE1. By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDE1. This is demonstrated for three industrial designs. In cases where all X-values have to be masked the novel approach is especially efficient.