X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
Efficient unknown blocking using LFSR reseeding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
X-tolerant Test Data Compaction with Accelerated Shift Registers
Journal of Electronic Testing: Theory and Applications
On compaction utilizing inter and intra-correlation of unknown states
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Masking of X-Values by Use of a Hierarchically Configurable Register
Journal of Electronic Testing: Theory and Applications
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This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and also increase the number of scan cells that are observed by the temporal compactors. Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. In this paper, the blocking logic gates for some groups of scan chains that do not capture unknowns are bypassed. Since all the scan cells in these scan chain groups are observed without specifying the corresponding bits in control patterns, fewer specified bits are required and more scan cells are observed. The seed size is further reduced by reducing numbers of specified bits in the densely specified control patterns. The proposed method can always achieve the same fault coverage that can be achieved by direct observation of scan chains. Experiments with large industrial designs clearly demonstrate that the proposed method is scalable to large circuits. Hardware overhead for the proposed blocking logic is very low.