X-Masking During Logic BIST and Its Impact on Defect Coverage

Authors:
Yuyi Tang;Hans-Joachim Wunderlich;Harald Vranken;Friedrich Hapke;Michael Wittke;Piet Engelke;Ilia Polian;Bernd Becker
Affiliations:
University of Stuttgart, Germany;University of Stuttgart, Germany;Philips Research Laboratories, The Netherlands;Philips Semiconductors GmbH, Hamburg, Germany;Philips Semiconductors GmbH, Hamburg, Germany;Albert-Ludwigs-University, Germany;Albert-Ludwigs-University, Germany;Albert-Ludwigs-University, Germany
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

Citing 0
Cited 17

Response compaction with any number of unknowns using a new LFSR architecture

Proceedings of the 42nd annual Design Automation Conference
Response shaper: a novel technique to enhance unknown tolerance for output response compaction

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient unknown blocking using LFSR reseeding

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors

Proceedings of the 43rd annual Design Automation Conference
Test response compactor with programmable selector

Proceedings of the 43rd annual Design Automation Conference
Fault detection and diagnosis with parity trees for space compaction of test responses

Proceedings of the 43rd annual Design Automation Conference
Synthesis of irregular combinational functions with large don't care sets

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Unknown blocking scheme for low control data volume and high observability

Proceedings of the conference on Design, automation and test in Europe
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis

IEEE Design & Test
A hybrid scheme for compacting test responses with unknown values

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Scan chain clustering for test power reduction

Proceedings of the 45th annual Design Automation Conference
X-tolerant Test Data Compaction with Accelerated Shift Registers

Journal of Electronic Testing: Theory and Applications
On compaction utilizing inter and intra-correlation of unknown states

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Split-masking: an output masking scheme for effective compound defect diagnosis in scan architecture with test compression

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A diagnosis algorithm for extreme space compaction

Proceedings of the Conference on Design, Automation and Test in Europe
Masking of X-Values by Use of a Hierarchically Configurable Register

Journal of Electronic Testing: Theory and Applications
Construction and Analysis of Augmented Time Compactors

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.