Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Heuristic minimization of BDDs using don't cares
DAC '94 Proceedings of the 31st annual Design Automation Conference
Graph driven BDDs—a new data structure for Boolean functions
Theoretical Computer Science
Binary decision diagrams and applications for VLSI CAD
Binary decision diagrams and applications for VLSI CAD
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques
IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
BOOM: a heuristic boolean minimizer
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Integration, the VLSI Journal
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Synthesis for Testability: Binary Decision Diagrams
STACS '92 Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
EFFICIENT PATTERN MAPPING FOR DETERMINISTIC LOGIC BIST
ITC '04 Proceedings of the International Test Conference on International Test Conference
X-Masking During Logic BIST and Its Impact on Defect Coverage
ITC '04 Proceedings of the International Test Conference on International Test Conference
On the complexity of minimizing the OBDD size for incompletely specified functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDD minimization using symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sibling-substitution-based BDD minimization using don't cares
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
A special logic synthesis problem is considered for Booleanfunctions which have large don't care sets and are irregular. Here, a function is considered as irregular if the input assignmentsmapped to specified values ('1' or '0') are randomly spread overthe definition space. Such functions can be encountered in the field of design for test. The proposed method uses ordered BDDs forlogic manipulations and generates free BDD-like covers. For the considered benchmark functions, implementations were found witha significant reduction of the node/gate count as compared to SISor to methods offered by a state-of-the-art BDD package.