Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the optimal variable ordering for binary decision diagrams
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Path-delay-fault testability properties of multiplexor-based networks
Integration, the VLSI Journal
Graph driven BDDs—a new data structure for Boolean functions
Theoretical Computer Science
Timed shared circuits: a power-efficient design style and synthesis tool
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficient Boolean Manipulation with OBDD's Can be Extended to FBDD's
IEEE Transactions on Computers
Synthesis for Testability: Binary Decision Diagrams
STACS '92 Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Some heuristics for generating tree-like FBDD types
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of irregular combinational functions with large don't care sets
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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Free binary decision diagrams (FBDDs) are an extension of ordered BDDs (OBDDs) that allow different variable orders along each path. FBDDs are a more efficient representation, while (nearly) all of the properties of OBDDs are kept. In some cases, even an exponential reduction can be observed.In this paper we first present an exact algorithm to find a minimal FBDD representation for a given Boolean function. To reduce the huge search space, a pruning technique is used. Since the exact algorithm is only applicable to small functions, also two heuristic algorithms for FBDD minimization are described. The first one can be seen as a modification of the exact algorithm which constructs the FBDD starting from the root nodes. The second one is based on an evolutionary algorithm.Experimental results show that in many cases significant improvements can be obtained, compared to the best known OBDD and FBDD sizes.