Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
IEEE Transactions on Computers - The MIT Press scientific computation series
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
ACORN: a local customization approach to DCVS physical design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A new method for verifying sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ACM Computing Surveys (CSUR)
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
IEEE Transactions on Computers
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fast exact minimization of BDDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Sampling schemes for computing OBDD variable orderings
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Using lower bounds during dynamic BDD minimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Accurate and efficient predicate analysis with binary decision diagrams
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Low power optimization technique for BDD mapped circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Integration, the VLSI Journal
Sample Method for Minimization of OBDDs
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
Design and test of the PowerPC 603 microprocessor
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Minimization of Ordered Pseudo Kronecker Decision Diagrams
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
IEEE Transactions on Computers
Fast functional evaluation of candidate OBDD variable orderings
EURO-DAC '91 Proceedings of the conference on European design automation
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Combining ordered best-first search with branch and bound for exact BDD minimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Combination of Lower Bounds in Exact BDD Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Technique for Estimating Signal Activity in Logic Circuits
Integrated Computer-Aided Engineering
Learning to order BDD variables in verification
Journal of Artificial Intelligence Research
A logically complete reasoning maintenance system based on a logical constraint solver
IJCAI'91 Proceedings of the 12th international joint conference on Artificial intelligence - Volume 1
On threshold BDDs and the optimal variable ordering problem
COCOA'07 Proceedings of the 1st international conference on Combinatorial optimization and applications
A memory efficient algorithm for network reliability
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
Finding compact BDDs using genetic programming
EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
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The ordered binary decision diagram is a canonical representation for Boolean functions, presented by Bryant as a compact representation for a broad class of interesting functions derived from circuits. However, the size of the diagram is very sensitive to the choice of ordering on the variables; hence for some applications, such as Differential Cascode Voltage Switch (DCVS) trees, it becomes extremely important to find the ordering leading to the most compact representation. We present an algorithm for this problem with time complexity O(n23n), an improvement over the previous best, which required O(n!2n).