Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the optimal variable ordering for binary decision diagrams
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-the-fly layout generation for PTL macrocells
Proceedings of the conference on Design, automation and test in Europe
Towards One-Pass Synthesis
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimization of the expected path length in BDDs based on local changes
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Combining ordered best-first search with branch and bound for exact BDD minimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Lower bounds for dynamic BDD reordering
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis and formal verification. The size of BDDs depends on a chosen variable ordering, i.e. the size may vary from linear to exponential, and the problem of improving the variable ordering is known to be NP-complete. In this paper we present a new exact branch & bound technique for determining an optimal variable order. In contrast to all previous approaches, that only considered one lower bound, our method makes use of a combination of three bounds and by this avoids unnecessary computations. The lower bounds are derived by generalization of a lower bound known from VLSI design. They allow to build the BDD either top down or bottom up. Experimental results are given to show the efficiency of our approach.