Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the optimal variable ordering for binary decision diagrams
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
Interleaving based variable ordering methods for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On-the-fly layout generation for PTL macrocells
Proceedings of the conference on Design, automation and test in Europe
Combination of Lower Bounds in Exact BDD Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quasi-Exact BDD Minimization Using Relaxed Best-First Search
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
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Reduced ordered Binary Decision Diagrams (BDDs) are frequently used in logic synthesis. In this paper we present a new algorithm to determine an optimal variable ordering of BDDs. In this, we combine ordered best-first search, i.e. the A-algorithm, with a classical Branch and Bound (B&B) algorithm. A operates on a state space, large parts of which are pruned by a best-first strategy expanding only the most promising states. Combining A with B&B allows to avoid unnecessary computations and to save memory.Experimental results demonstrate the efficiency of our new approach.