Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Fast functional simulation using branching programs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Telescopic units: increasing the average throughput of pipelined designs by adaptive latency control
DAC '97 Proceedings of the 34th annual Design Automation Conference
Post-layout logic restructuring for performance optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional simulation using binary decision diagrams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On-the-fly layout generation for PTL macrocells
Proceedings of the conference on Design, automation and test in Europe
Binary decision diagram with minimum expected path length
Proceedings of the conference on Design, automation and test in Europe
Minimizing the Number of Paths in BDDs
Proceedings of the 15th symposium on Integrated circuits and systems design
Performance Driven Synthesis for Pass-Transistor Logic
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Towards One-Pass Synthesis
Combination of Lower Bounds in Exact BDD Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evaluation of multiple-output logic functions using decision diagrams
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Average Path Length of Binary Decision Diagrams
IEEE Transactions on Computers
Prediction of area and length complexity measures for binary decision diagrams
Expert Systems with Applications: An International Journal
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In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial and is measured by the expected path length of the BDD.In this paper a new technique for BDD minimization with respect to the expected path length is suggested to reduce evaluation time. It is based on sifting and, unlike previous approaches, performs variable swaps with the same time complexity as the original sifting algorithm.Another field of application for BDDs is logic synthesis, often targeting Pass Transistor Logic (PTL) because of low power and low cost. A minimization of BDD size and chip area can lead to poor timing performances. We suggest to also use our method here, as the resulting BDDs show a very low maximal and average path delay. This supports the synthesis of high-speed PTL circuits at low area overhead.Exprimental results are given to show the efficiency of our approach.