Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams

Authors:
Magdy S. Abadir;Hassan K. Reghbati
Affiliations:
Univ. of Southern California, Los Angeles, CA;Simon Fraser Univ., Burnaby, Canada
Venue:
IEEE Transactions on Computers - The MIT Press scientific computation series
Year:
1986

Citing 6
Cited 4

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Functional Level Primitives in Test Generation

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Finding the Optimal Variable Ordering for Binary Decision Diagrams

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Classification of Faults in Synchronous Sequential Circuits

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Abstract

This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.