Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
Functional Level Primitives in Test Generation
IEEE Transactions on Computers
A Heuristic Algorithm for the Testing of Asynchronous Circuits
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
Deductive Fault Simulation with Functional Blocks
IEEE Transactions on Computers
Boolean Difference for Fault Detection in Asynchronous Sequential Machines
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
IEEE Transactions on Computers - The MIT Press scientific computation series
B-algorithm: a behavioral test generation algorithm
ITC'94 Proceedings of the 1994 international conference on Test
Hierarchical test generation using precomputed tests for modules
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On behavior fault modeling for combinational digital designs
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
| Hi-index | 14.98 |
This paper proposes an extension of the D-algorithm to functions described in computer hardware description languages. The proposed extension is applicable to both procedural and nonprocedural languages. Methods of D-propagation through the basic constructs of these languages and test generation for circuits containing functions described in CHDL's are discussed. The fault modes considered are function variables stuck at 0 or 1, control faults, and function faults with user-specified faulty behaviors.