Functional simulation in the lamp system
DAC '76 Proceedings of the 13th Design Automation Conference
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
Comparison of Parallel and Deductive Fault Simulation Methods
IEEE Transactions on Computers
A model and implementation of a universal time delay simulator for large digital nets
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
IEEE Transactions on Computers
Test Generation Algorithms for Computer Hardware Description Languages
IEEE Transactions on Computers
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This paper presents a method of propagating the effects of faults through functional blocks using the deductive (fault list) technique. An extension of the method is shown to be effective for simulating internal faults in functional blocks. The techniques presented here have been used for implementing the functional simulation capability in the Logic Analysis for Maintenance Planning (LAMP) System at Bell Laboratories.