Digital logic testing and simulation
Digital logic testing and simulation
The C programming language
Functional level simulation in FANSIM3 - algorithms, data structures and results
DAC '81 Proceedings of the 18th Design Automation Conference
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VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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This paper presents a mechanism to represent failures in complex combinational digital and VLSI designs at a high-level referred to as behavior fault models. The advantages of behavior fault modeling include early estimates of reliability of the design in the design process, reduced CPU time for fault simulation, and results that may be more comprehensive to the high-level architects. Digital and VLSI components are expressed in a high-level hardware description language and the fault models proposed in this paper are based on the failure modes of the language constructs of a generic hardware description language. In addition, fault models may be derived based on actual observed failures and multiple-input stuck-at faults that are also presented in this paper. This paper also reports on the evaluation of such fault models through a correlation of the behavior fault simulation results of representative example designs with fault simulation of equivalent gate-level representations in the presence of stuck-at faults.