Compiler Construction for Digital Computers
Compiler Construction for Digital Computers
An efficient method of fault simulation for digital circuits modeled from boolean gates and memories
DAC '77 Proceedings of the 14th Design Automation Conference
Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
Microcode development for microprogrammed processors
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Behavioral-Level Fault Simulation
IEEE Design & Test
A vertically organized computer-aided design data base
DAC '81 Proceedings of the 18th Design Automation Conference
On behavior fault modeling for combinational digital designs
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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This paper discusses the functional level logic simulation techniques used in the FANSIM3 simulator. The data structures for function evaluation and the algorithms used to simulate functional models are presented. The methods used to simulate datapaths and bussed signals are also discussed. Specific results, based on a year's experience with the simulator, are presented.