The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
Functional simulation in the lamp system
DAC '76 Proceedings of the 13th Design Automation Conference
F/LOGIC - An interactive fault and logic simulator for digital circuits
DAC '76 Proceedings of the 13th Design Automation Conference
Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
Multiple Experiment Environments for Testing
Journal of Electronic Testing: Theory and Applications
DAC '84 Proceedings of the 21st Design Automation Conference
Functional level simulation in FANSIM3 - algorithms, data structures and results
DAC '81 Proceedings of the 18th Design Automation Conference
A MOS/LSI oriented logic simulator
DAC '81 Proceedings of the 18th Design Automation Conference
A new test pattern generation system
DAC '80 Proceedings of the 17th Design Automation Conference
An accurate functional level concurrent fault simulator
DAC '80 Proceedings of the 17th Design Automation Conference
The incorporation of functional level element routines into an existing digital simulation system
DAC '80 Proceedings of the 17th Design Automation Conference
Computer-aided design of electrical circuits Simulation techniques (A Tutorial)
ACM '81 Proceedings of the ACM '81 conference
Digital logic simulation at the gate and functional level
DAC '79 Proceedings of the 16th Design Automation Conference
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The ability to predict the behavior of digital circuits containing faults is required for the verification and automatic generation of fault detection tests, and for the creation of fault dictionaries. The most common method of prediction is with a fault simulation program. Fault simulators simulate the fault-free (good) circuit and each of the possible faulty circuits. In most cases, the faulty circuit is assumed to contain only a single fault modeled as either a component input or output stuck-at-0 (SA0) or stuck-at-1 (SA1). Even so, a typical circuit may imply hundreds to thousands of possible faulty circuits. Reducing the cost of simulating large numbers of faulty circuits is the first major consideration in fault simulation.