The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
Integrated techniques for functional and gate-level digital logic simulation
DAC '73 Proceedings of the 10th Design Automation Workshop
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
An efficient method of fault simulation for digital circuits modeled from boolean gates and memories
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
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This paper discusses the main shortcomings of existing software test pattern generation systems and describes the development of a new system. The new system will be developed in two phases. The first phase is called the scan-in/scan-out test generation sub-system. This sub-system will be used for testing designs which have 100% scan-in/scan-out (reading or writing of every register from external world is possible). The second phase will include the development of efficient general functional models. The test generation system to be developed in the first phase will be updated to incorporate the capability of handling such models. The functional models include general-combinational, register, counter, ROM, RAM, and microprocessor. In this paper, only, an outline of some of the distinct features of the system will be described.