Modular requirements for digital logic simulation at a predefined functional level
ACM '72 Proceedings of the ACM annual conference - Volume 1
TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
DAC '72 Proceedings of the 9th Design Automation Workshop
A new approach to distributed functional fault modeling
WSC '86 Proceedings of the 18th conference on Winter simulation
IEEE Design & Test
Behavioral-Level Fault Simulation
IEEE Design & Test
Functional simulation and fault diagnosis
DAC '78 Proceedings of the 15th Design Automation Conference
LSI components modelling in a three-valued functional simulation
DAC '78 Proceedings of the 15th Design Automation Conference
A new test pattern generation system
DAC '80 Proceedings of the 17th Design Automation Conference
Functional simulation in the lamp system
DAC '76 Proceedings of the 13th Design Automation Conference
A new look at test generation and verification
DAC '77 Proceedings of the 14th Design Automation Conference
Fault modeling in a hierarchical simulator
DAC '77 Proceedings of the 14th Design Automation Conference
Concurrent fault simulation and functional level modeling
DAC '77 Proceedings of the 14th Design Automation Conference
Behavioral-level test development
DAC '79 Proceedings of the 16th Design Automation Conference
Developments in computer simulation of gate level physical logic
DAC '79 Proceedings of the 16th Design Automation Conference
Functional Level Primitives in Test Generation
IEEE Transactions on Computers
A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits
IEEE Transactions on Computers
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Digital simulation is defined as the process of exercising a realistic software model of a digital system, with sets of input stimuli, to generate signal behavior versus time. Simulation processes can be categorized by their simulation atom. Gate-level simulation 1,2,3,4 is simply one in which the atoms of simulation are gates. Functional simulation 5,6,7,8 simulates larger units, such as adders, decoders, registers, etc. It appears that gate-level simulators can perform accurate simulation4, 9. However, they present some operational limitations, such as the maximum number of gates that can be simulated. Further- more, the host computer time often becomes intolerable for large nets. An additional problem is encountered when the logical net is encoded for input to the simulator. Clerical errors in encoding the net, and their detection and correction, can cause costly delays. Finally, for gate-level simulators, MSI-LSI functional modules must be expanded to a gate-level description. The logical solution to the above limitations is the use of functional simulation techniques.