Fault modeling in a hierarchical simulator

  • Authors:
  • James J. Strunge

  • Affiliations:
  • -

  • Venue:
  • DAC '77 Proceedings of the 14th Design Automation Conference
  • Year:
  • 1977

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Abstract

A powerful fault modeling capability has recently been added to an established hierarchical logic analysis simulation and verification program. Both the simulator and modeling are described in detail.