Event manipulation for discrete simulations requiring large numbers of events
Communications of the ACM
BOLT-a block oriented design specification language
DAC '81 Proceedings of the 18th Design Automation Conference
A module level simulation technique for systems composed of LSI's and MSI's
DAC '78 Proceedings of the 15th Design Automation Conference
High-speed concurrent fault simulation with vectors and scalars
DAC '80 Proceedings of the 17th Design Automation Conference
The incorporation of functional level element routines into an existing digital simulation system
DAC '80 Proceedings of the 17th Design Automation Conference
An efficient method of fault simulation for digital circuits modeled from boolean gates and memories
DAC '77 Proceedings of the 14th Design Automation Conference
Digital logic simulation at the gate and functional level
DAC '79 Proceedings of the 16th Design Automation Conference
An extensible object-oriented mixed-mod functional simulation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Aquarius: Logic simulation on an Engineering Workstation
DAC '83 Proceedings of the 20th Design Automation Conference
Simulating pass transistor circuits using logic simulation machines
DAC '83 Proceedings of the 20th Design Automation Conference
An experimental MOS fault simulation program CSASIM
DAC '84 Proceedings of the 21st Design Automation Conference
BOLT-a block oriented design specification language
DAC '81 Proceedings of the 18th Design Automation Conference
A timing verification system based on extracted MOS/VLSI circuit parameters
DAC '81 Proceedings of the 18th Design Automation Conference
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
DAC '81 Proceedings of the 18th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
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A logic simulator capable of efficiently modelling complex MOS/LSI circuits is presented. The circuit is simulated at the combinational logic and transmission gate level using a set of six node-states. Gate models have inertial delay and assignable nominal rise and fall delays. Both unidirectional and bidirectional transmission gates are accurately simulated, and functional models are provided for ROM, RAM, etc.