Digital system simulation: Current status and future trends or darwin's theory of simulation
DAC '81 Proceedings of the 18th Design Automation Conference
PRIMEAIDS: An integrated electrical design environment
DAC '81 Proceedings of the 18th Design Automation Conference
Concurrent fault simulation and functional level modeling
DAC '77 Proceedings of the 14th Design Automation Conference
An efficient method of fault simulation for digital circuits modeled from boolean gates and memories
DAC '77 Proceedings of the 14th Design Automation Conference
Formal Verification of Fault Tolerance Using Theorem-Proving Techniques
IEEE Transactions on Computers
GARDEN—an integrated and evolving environment for ULSI/VLSI CAD applications
IBM Systems Journal
An extensible object-oriented mixed-mod functional simulation system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
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A new logic simulator called THEMISTM Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. THEMIS is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. This paper gives an overview of THEMIS and its use by design engineers.