Formal Verification of Fault Tolerance Using Theorem-Proving Techniques

  • Authors:
  • J. Kljaich, Jr.;B. T. Smith;A. S. Wojcik

  • Affiliations:
  • AT&T Bell Labs, Naperville, IL;Argonne National Lab, Argonne, IL;Michigan State Univ., East Lansing

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1989

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Abstract

A formal verification system based on the use of automated reasoning techniques is described to validate fault tolerance. An extended Petri net representation, called a flow net, is described together with the theorem-proving implementation of a rule-based system for manipulating system descriptions. Examples taken from the literature are used to illustrate the representation and the capabilities of the formal verification system under development.