Design of serviceability features for the IBM system/360
IBM Journal of Research and Development
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Design for Testability A Survey
IEEE Transactions on Computers
Testing for Intermittent Faults in Digital Circuits
IEEE Transactions on Computers
A Nine-Valued Circuit Model for Test Generation
IEEE Transactions on Computers
Test Generation Algorithms for Computer Hardware Description Languages
IEEE Transactions on Computers
Procedures for increasing fault coverage for digital networks
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
ATWIG, an automatic test pattern generator with inherent guidance
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
LSI logic testing: an overview
IEEE Transactions on Computers
Assessing system vulnerability using formal verification techniques
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
| Hi-index | 15.00 |
This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given.