Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
IEEE Transactions on Computers - The MIT Press scientific computation series
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
ACORN: a local customization approach to DCVS physical design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A new method for verifying sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ACM Computing Surveys (CSUR)
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Functional approaches to generating orderings for efficient symbolic representations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The Size of Reduced OBDD's and Optimal Read-Once Branching Programs for Almost all Boolean Functions
IEEE Transactions on Computers
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
IEEE Transactions on Computers
Solving Boolean Equations Using ROSOP Forms
IEEE Transactions on Computers
Free MDD-based software optimization techniques for embedded systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
OBDD Minimization Based on Two-Level Representation of Boolean Functions
IEEE Transactions on Computers
The nonapproximability of OBDD minimization
Information and Computation
Ordered binary decision diagrams
Logic Synthesis and Verification
Data structures for Boolean functions
Computational Discrete Mathematics
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Efficient Boolean Manipulation with OBDD's Can be Extended to FBDD's
IEEE Transactions on Computers
The complexity of minimizing and learning OBDDs and FBDDs
Discrete Applied Mathematics
Sample Method for Minimization of OBDDs
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
Automata and Binary Decision Diagrams
WIA '98 Revised Papers from the Third International Workshop on Automata Implementation
Algorithms and heuristics in VLSI design
Experimental algorithmics
From type inference to configuration
The essence of computation
Quasi-Exact BDD Minimization Using Relaxed Best-First Search
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
Simulation-Based Functional Test Generation for Embedded Processors
IEEE Transactions on Computers
Better upper bounds on the QOBDD size of integer multiplication
Discrete Applied Mathematics
Minimization of decision trees is hard to approximate
Journal of Computer and System Sciences
On the OBDD Complexity of Threshold Functions and the Variable Ordering Problem
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
Weighted A∗ search -- unifying view and application
Artificial Intelligence
Modeling Service Level Agreements with Binary Decision Diagrams
ICSOC-ServiceWave '09 Proceedings of the 7th International Joint Conference on Service-Oriented Computing
An efficient estimation of the ROBDD's complexity
Integration, the VLSI Journal
A microcanonical optimization algorithm for BDD minimization problem
IEA/AIE'07 Proceedings of the 20th international conference on Industrial, engineering, and other applications of applied intelligent systems
Implicit permutation enumeration networks and binary decision diagrams reordering
Proceedings of the 48th Design Automation Conference
Genetic algorithms for the variable ordering problem of binary decision diagrams
FOGA'05 Proceedings of the 8th international conference on Foundations of Genetic Algorithms
Dynamic segregative genetic algorithm for optimizing the variable ordering of ROBDDs
Proceedings of the 14th annual conference on Genetic and evolutionary computation
A Memory-efficient Bounding Algorithm for the Two-terminal Reliability Problem
Electronic Notes in Theoretical Computer Science (ENTCS)
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The ordered binary decision diagram is a canonical representation for Boolean functions, presented by R.E. Bryant (1985) as a compact representation for a broad class of interesting functions derived from circuits. However, the size of the diagram is very sensitive to the choice of ordering on the variables; hence, for some applications, such as differential cascode voltage switch (DCVS) trees, it becomes extremely important to find the ordering leading to the most compact representation. An algorithm for this problem with time complexity O(n/sup 2/3/sup n/) is presented. This represents an improvement over the previous best algorithm.