Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Finding the Optimal Variable Ordering for Binary Decision Diagrams
IEEE Transactions on Computers
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Reduction of OBDDs in linear time
Information Processing Letters
The implicit set paradigm: a new approach to finite state system verification
Formal Methods in System Design - Special issue on symbolic model checking
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Approximate reachability don't cares for CTL model checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Speeding up symbolic model checking by accelerating dynamic variable reordering
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Branching programs and binary decision diagrams: theory and applications
Branching programs and binary decision diagrams: theory and applications
Symbolic Model Checking
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Early Quantification and Partitioned Transition Relations
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
A Performance Study of BDD-Based Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Speeding Up Image Computation by Using RTL Information
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams
ISAAC '93 Proceedings of the 4th International Symposium on Algorithms and Computation
On the Existence of Polynomial Time Approximation Schemes for OBDD Minimization (Extended Abstract)
STACS '98 Proceedings of the 15th Annual Symposium on Theoretical Aspects of Computer Science
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
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