The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
A new partitioning scheme for improvement of image computation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Algorithms and heuristics in VLSI design
Experimental algorithmics
Ackermann encoding, bisimulations and OBDDs
Theory and Practice of Logic Programming
Decomposing image computation for symbolic reachability analysis using control flow information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based on OBDDs use a partitioned representation of the transition relation to keep the OBDD-sizes manageable. This paper presents a new approach that significantly increases the quality of the partitioning of the transition relation of controllers given in the hardware description language Verilog. The heuristic has been successfully applied to reachability analysis and symbolic model checking of real life designs, resulting in a significant reduction both in CPU time and memory consumption.