Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Speeding Up Image Computation by Using RTL Information
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Ackermann encoding, bisimulations and OBDDs
Theory and Practice of Logic Programming
State-set branching: Leveraging BDDs for heuristic search
Artificial Intelligence
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Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based on OBDDs use a partitioned representation of the transition relation to keep the OBDD-sizes manageable. This paper presents a new approach that significantly increases the quality of the partitioning of the transition relation of finite state machines. The heuristic has been successfully applied to reachability analysis and symbolic model checking of real life designs, resulting in a significant reduction in CPU time as well as in memory consumption.