DAC '97 Proceedings of the 34th annual Design Automation Conference
To split or to conjoin: the question in image computation
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
A new verification methodology for complex pipeline behavior
Proceedings of the 38th annual Design Automation Conference
Non-linear quantification scheduling in image computation
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Input Elimination and Abstraction in Model Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Border-Block Triangular Form and Conjunction Schedule in Image Computation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Random 3-SAT and BDDs: The Plot Thickens Further
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Algorithms and heuristics in VLSI design
Experimental algorithmics
The Compositional Far Side of Image Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
MUP: a minimal unsatisfiability prover
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Symbolic Techniques in Satisfiability Solving
Journal of Automated Reasoning
A system for the static analysis of XPath
ACM Transactions on Information Systems (TOIS)
Trading-off SAT search and variable quantifications for effective unbounded model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Towards scalable system-level reliability analysis
Proceedings of the 47th Design Automation Conference
Search vs. symbolic techniques in satisfiability solving
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
A model for integrating dialogue and the execution of joint plans
ArgMAS'09 Proceedings of the 6th international conference on Argumentation in Multi-Agent Systems
Computing argumentation in polynomial number of BDD operations: a preliminary report
ArgMAS'10 Proceedings of the 7th international conference on Argumentation in Multi-Agent Systems
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Hardware systems are generally specified as a set of interacting finite state machines (FSMs). An important problem in formal verification using Binary Decision Diagrams (BDDs) is forming the transition relation of the product machine. This problem reduces to conjuncting (or multiplying) the BDDs representing the transition relations of the individual machines, and then existentially quantifying out the set of input and output variables. The resulting graph is called the product graph. Computing the set of reachable states of the product graph is the central verification problem. In this paper, we discuss two related problems. The early quantification problem is the problem of interleaving multiplication of a set of BDDs with the quantification of a set of variables so that the size of the largest BDD encountered is minimized. We show that an abstraction of this problem is NP-complete, and provide heuristic solutions for it. In some cases, the size of the BDD representing the transition relation of the product graph is too large. The partitioned transition relations problem deals with partially combining the BDD脝s and quantifying as many variables as possible, so that the time for computing the set of reachable states of the product graph is minimized. We offer heuristic solutions to this problem based on our algorithms for early quantification. The algorithms have been implemented and good experimental results have been achieved.