Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
To split or to conjoin: the question in image computation
Proceedings of the 37th Annual Design Automation Conference
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Non-linear quantification scheduling in image computation
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Early Quantification and Partitioned Transition Relations
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Border-Block Triangular Form and Conjunction Schedule in Image Computation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Verification of Synchronous Sequential Machines Based on Symbolic Execution
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Automated validation of a communications protocol: the CCITT X.21 recommendation
IBM Journal of Research and Development
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FORCE: a fast and easy-to-implement variable-ordering heuristic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists
Formal Methods in System Design
The Compositional Far Side of Image Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Disjunctive image computation for software verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Lower bounds on the OBDD size of graphs of some popular functions
SOFSEM'05 Proceedings of the 31st international conference on Theory and Practice of Computer Science
On symbolic scheduling independent tasks with restricted execution times
WEA'05 Proceedings of the 4th international conference on Experimental and Efficient Algorithms
Saturation-based symbolic reachability analysis using conjunctive and disjunctive partitioning
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A symbolic approach to the all-pairs shortest-paths problem
WG'04 Proceedings of the 30th international conference on Graph-Theoretic Concepts in Computer Science
Exponential lower bounds on the space complexity of OBDD-Based graph algorithms
LATIN'06 Proceedings of the 7th Latin American conference on Theoretical Informatics
On symbolic OBDD-based algorithms for the minimum spanning tree problem
Theoretical Computer Science
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In symbolic model checking, image computation is the process of computing the successors of a set of states. Containing the cost of image computation depends critically on controlling the number of variables that appear in the functions being manipulated; this in turn depends on the order in which the basic operations of image computation--conjunctions and quantifications--are performed. In this paper we propose an approach to this ordering problem--the conjunction scheduling problem--that is especially suited to the case in which the transition relation is specified as the composition of many small relations. (This is the norm in hardware verification.) Our fine-grain approach leads to the formulation of conjunction scheduling in terms of minimum max-cut linear arrangement, an NP-complete problem for which efficient heuristics have been developed. The cut whose width is minimized is related to the number of variables active during image computation.We also propose a clustering technique that is geared toward the minimization of the max-cut, and pruning techniques for the transition relation that benefit especially from the fine-grain approach.