Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A machine program for theorem-proving
Communications of the ACM
Early Quantification and Partitioned Transition Relations
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Decomposition Techniques for Efficient ROBDD Construction
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Reliability-Aware Co-Synthesis for Embedded Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
A Dependability-Driven System-Level Design Approach for Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reliability-Centric High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Interactive presentation: Reliability-aware system synthesis
Proceedings of the conference on Design, automation and test in Europe
Reliable multiprocessor system-on-chip synthesis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Symbolic reliability analysis and optimization of ECU networks
Proceedings of the conference on Design, automation and test in Europe
Specification and design considerations for reliable embedded systems
Proceedings of the conference on Design, automation and test in Europe
An efficient reliability evaluation approach for system-level design of embedded systems
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and optimization of fault-tolerant embedded systems with hardened processors
Proceedings of the Conference on Design, Automation and Test in Europe
Symbolic system level reliability analysis
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) The BDDs exhaust available memory during their construction and/or (2) the final size of the BDDs is, sometimes up to several orders of magnitude, larger than the available memory. The contribution of this paper is twofold: (1) A partitioning-based early quantification technique is presented that aims to keep the size of the BDDs during construction at minimum. (2) A SAT-assisted simulation approach aims to deliver approximated results when exact analysis techniques fail because the final BDDs exhaust available memory. The ability of both methods to accurately analyze larger and more complex systems than known approaches is demonstrated for various test cases.