Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Generic ILP versus specialized 0-1 ILP: an update
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
System-level synthesis of adaptive computing systems
System-level synthesis of adaptive computing systems
Energy-aware deterministic fault tolerance in distributed real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
Reliability-Aware Co-Synthesis for Embedded Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
A Dependability-Driven System-Level Design Approach for Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Pueblo: A Modern Pseudo-Boolean SAT Solver
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Reliability-Centric High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
Interactive presentation: Reliability-aware system synthesis
Proceedings of the conference on Design, automation and test in Europe
Performance assessment of multiobjective optimizers: an analysis and review
IEEE Transactions on Evolutionary Computation
Exploiting data-redundancy in reliability-aware networked embedded system design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Towards scalable system-level reliability analysis
Proceedings of the 47th Design Automation Conference
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Incorporating graceful degradation into embedded system design
Proceedings of the Conference on Design, Automation and Test in Europe
Reliability-driven deployment optimization for embedded systems
Journal of Systems and Software
Reliability analysis for MPSoCs with mixed-critical, hard real-time constraints
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Symbolic system level reliability analysis
Proceedings of the International Conference on Computer-Aided Design
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Increasing reliability at a minimum amount of extra cost is a major challenge in todays ECU network design. Considering reliability as an objective already in early design phases has the potential to avoid expensive modifications in later design phases. Hence, there is a need for an appropriate optimization process and efficient analysis techniques to evaluate the found implementations. In this paper, we will show how symbolic techniques can be used to efficiently analyze and optimize such reliable systems. The contribution of this paper is (1) a symbolic reliability analysis that makes use of a partitioned structure function and (2) a symbolic optimization process based on binary ILP solvers. Our case study from the automotive area will show a significant speed-up using our analysis technique. Moreover, our optimization approach is able to offer implementations with considerably improved reliability at no additional costs as well as implementations with reduced costs without decreasing their reliability.