Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design space exploration of reliable networked embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Interactive presentation: Reliability-aware system synthesis
Proceedings of the conference on Design, automation and test in Europe
Reliable multiprocessor system-on-chip synthesis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Symbolic reliability analysis and optimization of ECU networks
Proceedings of the conference on Design, automation and test in Europe
Scheduling of fault-tolerant embedded systems with soft and hard timing constraints
Proceedings of the conference on Design, automation and test in Europe
Specification and design considerations for reliable embedded systems
Proceedings of the conference on Design, automation and test in Europe
Synthesis of fault-tolerant embedded systems
Proceedings of the conference on Design, automation and test in Europe
Symbolic voter placement for dependability-aware system synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Application-specific MPSoC reliability optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting data-redundancy in reliability-aware networked embedded system design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards scalable system-level reliability analysis
Proceedings of the 47th Design Automation Conference
Incorporating graceful degradation into embedded system design
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and optimization of fault-tolerant embedded systems with hardened processors
Proceedings of the Conference on Design, Automation and Test in Europe
Cost-effective safety and fault localization using distributed temporal redundancy
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A self-checking hardware journal for a fault-tolerant processor architecture
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
An ILP formulation for task scheduling on heterogeneous chip multiprocessors
ISCIS'06 Proceedings of the 21st international conference on Computer and Information Sciences
PPAM'05 Proceedings of the 6th international conference on Parallel Processing and Applied Mathematics
ACM Transactions on Embedded Computing Systems (TECS)
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As technology scales, transient faults due to single event upsets have emerged as a key challenge for reliable embedded system design. This paper proposes a design methodology that incorporates reliability into hardware-software co-design paradigm for embedded systems. We introduce an allocation and scheduling algorithm that efficiently handles conditional execution in multi-rate embedded systems, and selectively duplicates critical tasks to detect soft errors, such that the reliability of the system is increased. The increased reliability is achieved by utilizing the otherwise idle computation resources and incurs no resource or performance penalty. The proposed algorithm is fast and efficient, and is suitable for use in the inner loop of our hardware/software co-synthesis framework, where the scheduling routine has to be invoked many times.